LOW POWER DYNAMIC CMOS INVERTER AND SRAM CELL DESIGN USING LECTOR AND LECTOR-B TECHNIQUEVivek Harshey1,Pankaj Kumar Das2, Shivani Sharma3 |
A DEEP STACKING NETWORK MODEL OF ANTIVIRAL-HPV PROTEIN INTERACTION PREDICTIONB. Sharmila, A.V. Santhosh Babu |
DESIGN AND EVALUATION OF OPTIMIZED NETWORK-ON-CHIP (NOC) TOPOLOGIES FOR SYSTEM-ON-CHIP (SOC) ARCHITECTUREST. Suresh |
PERFORMANCE OPTIMIZATION OF INLINE EDFA-EYCDFA FOR MULTIPLE WAVELENGTH SERVICES IN OPTICAL COMMUNICATION SYSTEMS USING QUAD-SINGLE FORWARD AND TRI BACKWARD PUMPING TECHNIQUES Semmalar1, S Malarkkan2 |
PROVISIONING RESTORABLE VIRTUAL PRIVATE NETWORKS USING BARABASI AND WAXMAN TOPOLOGY GENERATION MODELR. Ravi |
LOAD PROFILE CLUSTERING: AN ALGORITHMIC APPROACH WITH IMPROVED REPLACEMENT IN BEE OPTIMIZATION ALGORITHMK. Kalyani1, T. Chakravarthy2 |