Abstract

Planar transmission line on silicon substrate imposes certain challenges at higher frequencies and measurement of the same employing wafer probing techniques needs accurate characterization. Wafer measurement provides information related with the device performance which in turn helps to minimize parasitic related with package and assembly. Wafer probing at higher frequencies imposes certain challenges more so ever on silicon substrate. Silicon substrate due to semiconductor in nature is a lossy medium for radio frequencies and standard wafer is not suitable for the realization of RF circuits. Present article demonstrate realization of planar transmission line on high resistivity silicon substrate by employing thick oxide layer. Both simulated and measured results are presented in this article and the CPW line fabricated with the proposed process results in ~1dB loss with better than 12dB return loss at Ka-band. Measurement techniques for the line characterization are detailed in this article along with transmission line characterization at Ka-band.