Abstract

A new era of linked devices has been brought about by the Internet of Things (IoT) revolution, and these devices heavily rely on AI to enable their increased functioning. There has been an increase in interest in the development of low-power edge AI processors for IoT devices to answer the requirement for lower power consumption of these devices. The design strategies, difficulties, and developments in the creation of such processors are examined in this work. The article starts out by highlighting the significance of low-power design for IoT devices before examining relevant design factors such system architecture, dataflow, and memory hierarchy. The different ways to cut back on power are then discussed, including power and clock gating, dynamic voltage/frequency scaling, and multi-core architectures. Finally, this presentation will review current developments in low-power VLSI design for edge AI processors, including heterogeneous-core processors and near-data processing. In conclusion, this paper offers a thorough overview of the most recent strategies and methods for creating low-power VLSI edge AI processors for Internet of Things devices.