Abstract

Comparator is an important building blocks used in analog-to-digital converters. Its function is to compare two analog inputs and delivers a logic value at the output. In this project an analysis on the delay of various dynamic comparators are presented. Based on the analysis a new dynamic comparator is designed for fast operations. Positive feedback mechanism is used to regenerate the analog input signal into full scale digital level. This design is a modification of conventional double-tail comparator. Addition of a few transistors to the conventional double-tail comparator results in remarkably reduced time delay. Kick-back noise of this comparator is also reduced. The large voltage variations in the internal nodes are coupled to the input nodes, which will disturb the input nodes-this is called kick-back noise. This is reduced by inserting switches before the input transistors of comparator. The performance of conventional comparator and proposed comparator circuits are evaluated based on Cadence 180nm CMOS process models.