Abstract

Estimating power consumption in CMOS VLSI circuits using supervised learning is the focus of this investigation. Unlike more conventional approaches like the SPICE circuit modelling that has been recommended, the proposed model does not assume a predetermined set of empirical equations or parameters. Unlike other technologies, and it doesn't require the user to pay attention to the circuit topology or the connectivity to provide precise results. An alternative interpretation with improved efficiency is suggested by the proposed design, but it will require a large amount of additional data for proper implementation. The proposed architecture has certain qualities that can improve power estimation for CMOS VLSI circuits.