In the era of 5g technology, it is needed to improve speed of the circuitry used in analog and digital hardware. Digital to analog conversion is an essential process, DAC is a vital circuitry utilized for the same in the electronic systems. Our proposed current-steering DAC (CS-DAC) offers suitability for both high speed and high-resolution requirements. This work claims memory less dynamic pipeline design technique and implementation of CS-DAC using pipeline technique. CS-DAC with and without memory-less dynamic pipeline design technique is implemented using 180nm Berkeley Short-Channel IGFET Model (BSIM) version 3.3 model file. The simulation results of CS-DAC with and without pipeline design technique also compared as well.
Shyamkumar Amrutlal Pankhaniya, Jayeshkumar C. Prajapati, Anju Murlibhai Vasdewani
Government Engineering College, Patan, India
Digital to Analog Converter (DAC), Current-Steering DAC (CS-DAC), System on Chip (SOC), Differential Non-Linearity (DNL), Integral Non-Linearity (INL), Spurious-Free Dynamic Range (SFDR) and Signal-to-Noise and Distortion Ratio (SNDR)
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 10 , Issue: 4 , Pages: 1945 - 1951 )
Date of Publication :
January 2025
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182
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