Abstract

This paper presents an 8T Schmitt Trigger (ST) based SRAM design to improve the read stability and power dissipation of conventional 6T SRAM cell. The ST based SRAM cell incorporates built-in feedback mechanism in order to attain robust read operation. The read stability of the cell is 2.5× higher than that of 6T SRAM cell at 1.8V and it can retain data even at a lower Vmin of 0.3V. Also, power consumption is reduced by 22% compared to 6T SRAM design. The layout drawn using 120nm technology rule shows that the 8T ST SRAM occupies 1.2× higher area compared to 6T SRAM cell. Peripheral circuits for the 8T ST SRAM are introduced. Except the precharge circuit and basic SRAM cells, the remaining part of the circuitry is same for both single bit 6T and 8T ST SRAM array design. The single bit 8T ST SRAM array consumes less power and area in nano-scaled technologies. The proposed design was simulated in Mentor Graphics ELDO using TSMC 180nm technology.