DESIGN AND OPTIMIZATION OF HETEROGENEOUS SYSTEM-ON-CHIP ARCHITECTURE USING SELF-ADAPTIVE NEURAL NETWORK ACCELERATOR
Abstract
In response to the escalating demand for energy-efficient and high-performance computing, this research explores the design and optimization of a heterogeneous System-on-Chip (SoC) architecture employing a self-adaptive neural network accelerator. Addressing the current limitations in heterogeneous SoC designs, we identify the need for dynamic adaptation to varying workloads. Our proposed methodology integrates a self-adaptive neural network accelerator that autonomously adjusts its architecture based on real-time workload characteristics. Through extensive simulations, we demonstrate significant improvements in both energy efficiency and performance compared to traditional static architectures. This research bridges the existing gap in adaptive computing, providing a promising avenue for future energy-efficient heterogeneous SoC designs.

Authors
B. Ebenezer Abishek1, C. Sharanya2, S. Gopalakrishnan3, J. Jency Rubia4
Vel Tech Multi Tech Dr.Rangarajan Dr.Sakunthala Engineering College, India1, Vels Institute of Science, Technology and Advanced Studies, India2, Sengunthar Engineering College, India3, Vel Tech Rangarajan Dr.Sagunthala R&D Institute of Science and Technology, India4

Keywords
Heterogeneous System-on-Chip, Neural Network Accelerator, Self-Adaptive Architecture, Energy Efficiency
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01427800000000
Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 9 , Issue: 4 , Pages: 1705 - 1710 )
Date of Publication :
January 2024
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180
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