VLSI ARCHITECTURE FOR ERROR DETECTION AND CORRECTION BASED ON XOR AGAINST MULTIPLE CELL UPSETS WITH REDUCED REDUNDANT BITSV Bhanumathi, M Sunandini |
A PROPOSED NOVEL ARCHITECTURE OF EC CONTROL SYSTEM USING IEEE 802.11n NETWORK AT ITER-INDIA GYROTRON TEST FACILITYDeepak Mandge1, Nagendra P Gajjar2, Vipal Rathod3, Ronak Shah4, Rajvi Parmar5, S Laxmikanth Rao6 |
PERFORMANCE ANALYSIS OF SET PARTITIONING IN HIERARCHICAL TREES (SPIHT) ALGORITHM FOR A FAMILY OF WAVELETS USED IN COLOR IMAGE COMPRESSIONA. Sreenivasa Murthy, K.N. Ramesh, Y.A. Mamatha |
EFFICIENT FREQUENT ITEMSET DISCOVERY THROUGH HIERARCHICAL HUFFMAN ENCODINGDai Xin, Hao Xue |
RESILIENT SCHEME AGAINST REDUCTION OF QUALITY (ROQ) DISTRIBUTED DENIAL OF SERVICE ATTACK IN MANETS.A. Arunmozhi1 and Y. Venkataramani2 |
HEALTHODE: NEURAL DISCRETIZED DYNAMICS FOR ROBUST FORECASTING OF PATIENT WELLNESS Shrutibahen Patel |