Abstract

Wearable devices demand ultra-low-latency computation to support real-time applications such as health monitoring, motion tracking, and augmented reality. Field Programmable Gate Arrays (FPGAs) offer a reconfigurable platform for energy-efficient and high-performance computing in such environments. Traditional hardware-software co-design methods are time-intensive due to complex simulation loops and design space exploration (DSE). This becomes a bottleneck for real-time embedded applications where latency and power constraints are critical. This research proposes a Neural Surrogate-Assisted Co-Design (NSCD) framework that accelerates the DSE process by replacing expensive simulations with predictive neural models. The framework integrates lightweight surrogate models trained on hardware and software profiling data to predict latency, power, and throughput across FPGA configurations. It enables rapid convergence to optimal co-design solutions under timing and energy constraints. Experiments on a wearable motion classification task using the Xilinx Zynq-7000 FPGA demonstrate that NSCD reduces DSE time by over 70% while achieving 15–22% lower latency and 18% energy savings compared to traditional exhaustive search and heuristic-based co-design approaches.