Abstract

This paper proposes and investigates a new architecture of PNPN TFET by using 2-D ATLAS Device Simulation Software TCAD Tool. The source pocket plays a crucial role in increasing the ON-state current through Tunnel FET. In order to enhance the source pocket characteristics, the source pocket is divided laterally into high and low concentration source pockets without modulating its width (LP). This modification results in reduction of tunnelling width (?), thereby increasing the significant amount of lateral electric field and suppressing the horizontal electric field, which in turn enhance the tunnelling probability as well as tunnelling rate. This proposed structure is a promising candidate for getting higher ON-state current (Ion), higher current ratio (Ion/Ioff), lower threshold voltage (VT) and reduced steepness sub-threshold slope (SS). These parameters are calculated with respect to conventional PNPN TFET and hetero-dielectric BOX (HDB) PNPN TFET, which enable the device to be operated efficiently with lower power consumption.