Abstract

This paper presents a new adaptive biasing technique for improving the slew rate of CMOS opamps without increasing the power consumption. All the proposed circuits for adaptive biasing are implemented using a current subtractor and NMOS based circuit. Further, the input stage of opamp in proposed circuits were substituted by Flipped Voltage Follower circuit and Self Cascode structure to study their effects on adaptive biasing circuits. The conclusion of this work is that there is a notable enhancement in slew rate, settling time and power dissipation in proposed adaptive biasing techniques. All the circuits have been designed using 180nm CMOS technology and simulated using cadence virtuoso.