Abstract

In floorplanning, our aim is to determine the relative locations of the blocks in the chip and the objective is to minimize the floorplan area, wirelength. Generally, there are so many strategies in VLSI floorplanning like area optimization, wirelength optimization, power optimization, temperature optimization and etc. This paper concentrates on area optimization. The goal of the physical design process is to design the VLSI chip with minimum area. The primary idea is to minimize the floorplan area by reshaping the blocks which are present inside the floorplan in order to attain the minimum area with less computational time. Proposed problem is redefined with an efficient meta-heuristic as Simulated Annealing algorithm which will provide optimal solution with less computation time. The proposed algorithm has been tested by using set of benchmarks of Microelectronics Centre of North Carolina (MCNC).The performance of the proposed algorithm is compared with other stochastic algorithms reported in the literature and is found to be efficient in producing floorplan with minimal area. The performance of the proposed algorithm seems to be better than the existing algorithms.