Abstract

6T SRAM cell has fast differential sensing and offers high density but read-write conflict exists which puts restrictions on the sizing of the devices. This degrades the stability in read mode with the declining supply voltage. To eliminate it, 8T SRAM cell incorporates decoupled read port to enhance the read stability. But it suffers from the datadependent leakage which deteriorates the Read Bit Line swing. So, the data-independent and low leakage power is necessary to enhance the read sensing margin. To achieve the above, a new 10T SRAM cell is proposed which incorporates data independency and low leakage power. At the worst process corner FF, there is a reduction of 13.7%, 27.7% in leakage power of P10T SRAM cell compared to 10T1 SRAM and 10T2 SRAM cells at 0.9V while holding 0. The variation of supply voltage and the temperature has been studied on the leakage power. All the designs were implemented in 45nm technology and Post Layout simulation has been carried in Cadence Virtuoso.