Abstract

The following manuscript proposes a modification to the existing PFAL based adiabatic structure called 2Phase PFAL for its operation on two phase sinusoidal power clocks and lower power dissipation. Sinusoidal shaped power clocks are easier to design and can be used to operate the adiabatic circuit in two phases. This proves to be advantageous as it reduces the on-chip routing complexity and density of the power-clock logic. Moreover usage of a two phase structure over a four phase structure for adiabatic operation reduces the phase consistency relationship requirement among the power clocks to realize the potential adiabatic gains. Conventional PFAL based approach requires the usage of buffers both at the input and output stages, increasing the buffer requirement. The proposed circuit is advantageous as it operates on two phases, reducing the buffer requirement leading to savings in area and power. Simulations using a standardized test bench have been performed for CMOS, PFAL and Proposed Logic based Inverter, Inverter Chain, NAND, NOR, XOR and XNOR structures. The results show that the proposed structure require less power as compared to its nearest competitors. Lower power dissipation with phase reduction, ease of power clock generation, reduced routing complexity and phase consistency relations among the power clocks make the proposed logic an suitable candidate for use in low power digital devices operating at low frequencies such as radio-frequency identifications (RFID`s), smart cards, and sensors.