Abstract

At the current deep submicron and nanometer level, the leakage power is becoming the major contributor to overall power consumption in modern VLSI circuits. This research paper presents a novel approach to reducing leakage power by inserting two leakage transistors in the middle of pull-down and pull-up paths. Out of these two leakage transistors, one is the PMOS transistor, and another one is the NMOS transistor. This research work presents a dynamic CMOS inverter and 6T SRAM cell with and without transmission gate (TG) to reduce leakage power using the LECTOR and LECTOR-B techniques. The Cadence Virtuoso simulation tool is used to presents the results in terms of static power. Using the 45-nm technology node, the performance in terms of static power is analyzed. It is observed that using LECTOR and LECTOR-B techniques, the overall reduction in static power is 26% and 20%, respectively, compared to the conventional design for SRAM cell. Similar improvements are also noted for dynamic CMOS inverter and TG SRAM cell.