Abstract

In this paper, the Markov M/D/1/B queuing model that has been created will be discussed. One approach to evaluating the effectiveness of a router is to use a model of a queue that is analogous to the one that we presented above. Having said that, this can be accomplished in a variety of different ways. According to the results of the studies, altering the service rate has a discernible bearing not only on the amount of data the system processes but also on the effectiveness of its operation. For the purpose of demonstrating the viability of our methodology, we built an output-queuing router using FPGA. When utilising this method, it is possible to observe that the queues and the control unit of the router take up an excessive amount of space on the silicon. This is a consequence of the fact that this method is utilised. The difference in effectiveness between a theoretical model and a real prototype is only 2%. This is a very small margin. The study implemented our design on a Xilinx FPGA Vertix II Pro family 100K chips. In the following subsections, we present the router FPGA synthesis results and evaluate its performance.