Abstract

Multiplication is critical for computers linked to cryptography or the ALU function. It consumes more chip area and time than the other ALU functions. The speed of the processor, coprocessor, or embedded system may depend on the multipliers’ speed. Nowadays, designing a small, high-performance multiplier is a critical challenge in computer architecture, cryptographic hardware design, and embedded system design. One of the better solutions is developing a digital multiplier design based on Vedic mathematical formula. The performance of the Digital Vedic Multiplier (DVM) is entirely dependent on the adder network. DVM is evaluated here using KS Adder and CLA Adder. There are several publications on this topic, but the primary shortcoming is that they focus exclusively on the DVM without addressing the influence of the adder circuit. This work aims to investigate the impact of the adder circuit on the space-speed trade-off inherent in the design of the DVM.