vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff96222c000000c1f8000001000b00
Multi-gate MOSFETs have successfully enabled the extension of CMOS technology scaling in the nanoscale regime. Suppression of short channel effects (SCEs) and carrier transport enhancement are the two prime factors that matter the most for the improvements in digital CMOS technology. Multi-gate transport leads to suppression of SCEs and mobility improvement leads to carrier transport enhancement. Continuous scaling of device channel length in the nanoscale regime invites for the inclusion of scattering theory physics. The proposed work discusses the diverse carrier transport mechanisms occurring in Multi-gate MOSFETs in different channel length regimes. Further, a comparative analysis of carrier transport in long, short and ultra-short channel Multi-gate devices is done. The work also discusses the validity of the transport models and their scaling restrictions in different regimes. The simulation results demonstrate physical accuracy and continuity of the proposed models in the respective channel length regimes.