Abstract

The implementation of 2D DWT is a challenge using CMOS technology for miniature device (65nm minimum). For applications like biomedical engineering the area and power consumption are to be reduced. The Limitation of Existing methods is addressed in this paper and an alternate method of implementing the algorithm is presented. In addition, problems lie on high critical path due to the presence of multipliers, Delay is high due to critical path and computation, Execution Speed is less due to multipliers in existing DWT architecture. On the other hand below 45nm the problems in CMOS devices on leakage current, limitations on threshold voltage, short channel effect, high field effects and dopant number fluctuations, and interconnect delays are faced. The work focuses on designing the 2D DWT architecture using FinFETs which has leakage power superiority and power minimization. The proposed VLSI architecture for lifting based 2D-Discrete wavelet transforms (DWTs) using FinFET in 32nm technology is efficient when compared to the existing convolution- based architecture. The Predict and update stage of lifting based DWT without multiplier is implemented using HSPICE. The critical delay due to multiplier usage is eliminated. The multiplier less design enhances the performance of the system.