A MOSFET CAPACITANCE MODEL FOR ALL GATE BIASING

Abstract
The present paper describes a modeling of the capacitance of a MOSFET operated in all regions, i.e. subthreshold linear and saturation. The model is based on the electric charges behavior under a dynamic gate biasing and sweeping the Si-SiO2 interface from deep accumulation to deep inversion. The model is based on the charge model and our I-V current model developed earlier. The proposed model which is obtained after mathematical analysis has been compared to the classical model valid each operating region, i.e., accumulation subthreshold and inversion. It has been found to be in quiet good agreements for the linear and saturation regions. In addition, our model expresses the capacitance in the subthreshold region which is not explicitly described by the corresponding classical model. The experimental data obtained on research devices are found to suite our model in all the three regions.

Authors
Ahcene Lakhlef, Arezki Benfdila
Mouloud Mammeri University of Tizi-Ouzou, Algeria

Keywords
MOSFET, I-V Current Model, Capacitance Model, Gate Biasing
Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 4 , Issue: 4 )
Date of Publication :
Januray 2019
DOI :

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