This paper focuses on the design of a 14 transistor one bit adder cell designed using CNTFET 32nm Technology to address the power and speed issues of high performance computational systems. The performance metrics of the proposed adder cell is compared by benchmarking with conventional full adder design, Transmission gate based full adder and Shannon’s expression based full adders using CNTFET technology. The proposed design has lesser delay and very low power consumption. The design embraces Stanford 32nm planar CNTFET library model with a power supply of 1 volt and single walled CNT. Extensive simulation has been carried out on the adder cells considered and the parameters such as power, delay and PDP are investigated. The effect of temperature variation on the power consumption of proposed 14T adder cell is also observed to examine the robustness. The simulation results demonstrate that the proposed adder delivers stable output drivability with substantial diminution in the leakage power.
Balaji Ramakrishna S, Aswatha A R
Dayananda Sagar College of Engineering, India
CNTFET, Adder Cell, Full Adder, Low Power, PDP | Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 3 , Issue: 3 )
Date of Publication :
October 2017
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