vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff158f1f0000000018050001000300 The Scaling of conventional Complementary Metal Oxide Semiconductors (CMOSs) has been facing problems such as short channel effect due to hot electron effect and leakage power. Fin Field Effect Transistor (FinFET) is considered as solution to this issue. Binary system occupies large area there for the circuit complexity is increasing on a VLSI chip and thus degrading the performance of binary system. Multi valued logic MVL is considered as solution to this issue. In this paper, to minimize short channel effect and reduce circuit complexity on a VLSI chip I have designed FinFET based ternary basic gates (T-NOT, ST-NAND, ST-NOR, ST-AND and ST-OR). FinFET is classified in to two types based on gate structure: 1) Short Gate FinFET (SG-FinFET) and 2) Independent Gate FinFET (IG-FinFET). The proposed ternary logic gates are design using SG-FinFET. Simulation is performed with Tanner EDA tool. The proposed design has achieved good reduction in the circuit element count.
Makani Nailesh Kishor1, Satish S. Narkhede2
Gujarat Technological University, India1, Pune Institute of Computer Technology, India2
Fin Field Effect Transistor, Multi Valued Logic, Multi Valued Logic Gates, Ternary Gates
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 2 , Issue: 2 , Pages: 254-260 )
Date of Publication :
July 2016
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