vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff37e51b000000f61e000001000500
The objective of this research paper is to analyze and estimate the reliability of an inverter circuit and two CMOS gate interconnect circuit , a combination of two inverters connected with an RC model as an interconnect structure using cadence virtuoso tool utilizing at gpdk 45 nm technology. Reliability in terms of electronic circuit basically depends on hot-carrier injection, negative biasing temperature instability, positive biasing temperature instability and slightly due to the effect of time-dependent gate oxide breakdown. The inverter used in this work is without any load effect at output terminal and further a capacitive load has been applied at the output terminal. The reliability predictions are done by comparing power, delay and output voltage after a specific interval of time.