This study delves into the incorporation of triboelectric nanogenerators (TENGs) in Very Large Scale Integration (VLSI) design, specifically focusing on their impact on delay analysis within multiplexer circuits. The conventional approach to VLSI design encounters challenges related to power consumption and delay, necessitating innovative solutions. The research gap lies in the limited exploration of TENGs in VLSI circuits, particularly multiplexers, and their potential to enhance performance. The proposed methodology involves the integration of TENGs within multiplexer circuits to harness energy and mitigate delay issues. TENGs, known for converting mechanical energy into electrical energy, offer a unique avenue to address the power-delay trade-off in VLSI design. The study employs rigorous simulations and analyses to evaluate the delay characteristics of multiplexer circuits with and without TENG integration. The results showcase promising reductions in delay and improvements in power efficiency through TENG integration. The findings provide valuable insights into the feasibility and benefits of incorporating triboelectric nanogenerators in VLSI designs, offering a novel perspective for addressing performance challenges in modern electronic systems.
Avinash G. Mahalle1, Pravin Prakash Adivarekar2, M. Kumar3, Virendra Jain4, Davinder Kumar5
Prof. Ram Meghe Institute of Technology and Research, India1, A P Shah Institute of Technology, India2, Chettinad College of Engineering and Technology, India3, Mandsaur University, India4, Micron semiconductor Inc, Idaho, United States5
Triboelectric Nanogenerator, VLSI Design, Multiplexer Circuit, Delay Analysis, Power Efficiency
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 9 , Issue: 4 , Pages: 1700 - 1704 )
Date of Publication :
January 2024
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248
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