vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff7dce310000007749010001000800 Deep Submicron Architectures (DSAs) are utilised to design integrated circuits (ICs) that are both low power and high speed. In this paper, we present a new approach to Deep Genetic Approach (DGA), which is a hybrid error reduction LOA that is designed to increase the computation accuracy of the LOA. This approach is based on the use of OR and XOR to obtain an approximate adder for the inputs that have the (n-k-1)th least significant bit of both inputs to further reduce the output errors. The power consumption and latency of various implementations of the planned DGA are analysed. It has been discovered that using MTCMOS and GDI together leads to a large reduction in leakage power as well as an improvement in latency. In addition, the power delay product (PDP) of the CSA is one of the variables that can be significantly improved by adopting the way that was proposed.
Maram Ashok1, N. Jagadeeswari2, K. Balaji3, M. Ramkumar4
Malla Reddy Institute of Engineering and Technology, India1, Thanthai Periyar Government Institute of Technology, India2, SSM College of Engineering, India3, Knowledge Institute of Technology, India4
VLSI, Adder, Prediction, Mechanism, Genetics, High-Speed
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 9 , Issue: 1 , Pages: 1525 - 1528 )
Date of Publication :
April 2023
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202
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