Abstract

This paper briefs an implementation of different CIC filter architectures for decimation. The different decimation filter structures are implemented using cascaded integrator-comb filter to work for the down sampling ratio of 8. The prototype is designed with MATLAB Simulink model and it is converted to VHDL code using Xilinx system generator. Prototype is implemented in Virtex V- XC5VLX110T-3ff1136 FPGA kit and simulation results and device utilization reports are generated and tabulated. Finally different architectures are compared using number of used LUTs, Registers, Power consumption etc.