Abstract

The IEEE-754 single-precision floating-point multiplication is a fundamental arithmetic operation in modern digital systems and is widely used in DSP, graphics and machine learning accelerators. The demand for computations is increasing day by day, so the hardware realization of these operations in terms of logic utilization and signal propagation delay is of utmost importance. This paper presents a highly optimized design of 32-bit floating point multiplier for FPGA. The design approach is purely structural with high emphasis on mantissa data-path. The proposed architecture uses a highly specialized Radix-4 Modified Booth Encoding algorithm to reduce the number of partial products by half. This leads to a substantial reduction of hardware overhead. We also propose a new narrow 25-bit Partial Product Generator and a dedicated wire-routed Two-Shift stage, which achieves around 50% gate reduction in the generation phase by eliminating redundant sign-extensions. A bounded Dadda reduction tree compresses the first 14-row matrix (13 partial products and one structural sign-correction row). The proposed tree is approximately 41% narrower than conventional 88-bit designs, thereby reducing internal interconnect and routing overhead. The last addition is done by 52-bit Carry Propagate Adder. The proposed architecture is synthesized on Xilinx Artix-7 platform and the results show the significant area saving and the deeply reduced latency, which makes the architecture very effective for high-performance computational applications with resource constraints.

Authors

Shyam Peraka, Pusuluri Vinod Babu, Ramineni Vardhan Naidu, Ravanam V.S.M. Sesha Suresh, Kuna Yashaswini, Shaik Gowsiya
Rajiv Gandhi University of Knowledge Technologies, India

Keywords

IEEE 754, Floating-Point Multiplier, Radix-4 Modified Booth Encoding, Dadda Tree, FPGA Design