Abstract

This paper presents a detailed performance analysis of a CMOS charge pump (CP) designed for phase-locked loop (PLL) applications in RF and microwave systems, specifically targeting the S-band and C-band frequency ranges. Implemented in 90 nm CMOS technology, the proposed CP employs two complementary transmission gates to effectively suppress charge sharing and clock feed through, thereby enhancing accuracy and stability. Operating from a 1.0 V supply, the design achieves a total power consumption of 223 µW. The circuit delivers an output current of 291 µA in charging mode and 267 µA in discharging mode, maintaining a linear output voltage range from 0 V to 1 V. Designed to operate at 5 GHz, the CP demonstrates high-speed operation with low power dissipation, making it well-suited for modern high-frequency PLL architectures. Comprehensive simulation results highlight the proposed CP’s capability to meet the stringent performance requirements of low-power, high-speed RF applications.

Authors

Parul Trivedi, Onkesh, Madhu Dwivedi, Deepa Prajapati
Veer Bahadur Singh Purvanchal University, India

Keywords

CP for PLL, RF/Microwave System, High Operating Frequency CP