Abstract

The paper entails the design of a 16-bit multiplier with the combined application of Karatsuba algorithm and the Urdhva- Tiryagbhyam (UT) theorem and the implementation of the multiplier architecture in Modified-Gate-Diffusion-Input (Mod-GDI) cells for improving the area and power constraints in the proposed novel hybrid multiplier.

Authors

Bobby Nelson, Ravi Tiwari
Shri Shankaracharya Technical Campus, India

Keywords

Area-Efficient, GDI, Karatsuba Algorithm, Multiplier, Urdhva- Tiryagbhyam Theorem