Abstract

FP-Floating point arithmetic unit is the widely used application in Digital Signal Processing (DSP), which is an alternative of the logarithmic number system. When compared to the square root operations, the addition, subtraction, multiplication and division are more challenging tasks. In accordance with this reason, few structures were developed in the existing literatures concerning the DSP. But, it has some drawbacks which includes increased memory usage, delay and power consumption. To overwhelm these issues, a Semi Parallel Folded Add-Shift (SPFAS) architecture is carefully designed by making use of minimized components is introduced. Here, the folded Discrete Tchebichef Transformation (DTT) multiplier is integrated with SPFAS forming the novelty in the circuit used in this work in order to find the output register. Moreover, there is no need to add any separate block for performing subtraction operation because of the integration undertaken. The main advantage of this concept is that it reduces the size of Digital Signal Processing (DSP) unit with minimum usage of logical components and registers. Also, the structure of shifter and adder are changed to reduce the accumulator size, Flip Flop (FF) and Look Up Table (LUT). In experiments, the performance of the proposed SPFAS with DTT architecture is evaluated and compared in terms of delay, area, latency, cycles, RAM, LUTs, slice and FFs. On investigating, we could infer that this devised architecture design need only lesser usage components of 5979 instead of 8702.

Authors

M. Kiruba¹, V. Sumathy², K.N. Vijeyakumar³
SNS College of Technology, India¹, Government College of Engineering, Dharmapuri, India², Dr. Mahalingam College of Engineering and Technology, India³

Keywords

SPFAS-Semi Parallel Folded Add-Shift architecture, DTT-Discrete Tchebichef Transformation, FPPE-Floating Point Processing Element, DSP-Digital Signal Processing, and FFs-Flip Flops