Abstract

Wearable Edge Artificial Intelligence (AI) devices have become fundamental components of next-generation healthcare, industrial monitoring, and intelligent human-machine interaction systems. These platforms require real-time inference, ultra-low latency, minimal power consumption, and compact hardware footprints. Field Programmable Gate Arrays (FPGAs) have emerged as attractive deployment platforms because they provide reconfigurable hardware acceleration while maintaining energy efficiency. However, identifying an optimal hardware-software partition and neural network architecture remains a computationally intensive and highly complex optimization problem. Existing FPGA hardware-software co-design frameworks generally depend on manually engineered architectures or computationally expensive Neural Architecture Search (NAS) techniques. These approaches often ignore global feature dependencies, resource-aware optimization, and dynamic adaptation required for wearable edge intelligence, resulting in suboptimal latency, energy efficiency, and hardware utilization. This paper proposes a novel Transformer Assisted Neural Architecture Search for Hardware Software Co-design (TANAS-HSC) framework. The proposed framework integrates Transformer-based global dependency learning with a multi-objective Neural Architecture Search strategy to automatically identify optimal neural architectures while simultaneously optimizing FPGA hardware-software partitioning. The optimization jointly considers inference accuracy, latency, power consumption, FPGA resource utilization, and memory bandwidth constraints. An adaptive co-design scheduler further refines hardware mapping through iterative resource-aware optimization. Experimental evaluation demonstrates that the proposed TANAS-HSC framework achieves 98.74% classification accuracy, improving performance compared with DARTS, ENAS, and HA-NAS-based approaches. The framework reduces inference latency to 18.6 ms, achieving approximately 36.30% lower delay than hardware-aware NAS methods. Furthermore, TANAS-HSC minimizes energy consumption to 1.94 J, improves FPGA resource utilization efficiency to 93.82%, and reduces architecture search time by 53.97% compared with conventional NAS techniques. These results validate the effectiveness of Transformer-guided architecture exploration and adaptive hardware-software co-design for efficient wearable edge AI deployment.

Authors

B. Sathananth¹, Pitty Nagarjuna²
V.S.B. College of Engineering Technical Campus, India¹, Indian Institute of Science, Bengaluru, India²

Keywords

Transformer, Neural Architecture Search, FPGA Co-design, Wearable Edge AI, Hardware Software Optimization