Abstract

Traditional parallel prefix adders ensure faster carry propagation but may cause routing issues and additional overhead in interconnect when implemented on FPGAs. In order to overcome such limitations, this paper proposes an FPGA-friendly 32-bit Hybrid Approximate Parallel Prefix Adder (HAPPA), which utilizes routing-balanced prefix adder design approaches as well as placement-based methods to implement the low-power multimedia and image processing systems. The suggested design architecture uses three different computation regions: 13-bit Kogge-Stone prefix adder network for high-speed carry propagation in most significant bits, 15-bit Knowles prefix adder to compromise between routing complexity and delay performance and reference- inspired 4-bit approximate adder for reduced logic and switching activities in least significant bits computation. Localized PBLOCK-based floor planning as well as hierarchy-preserving placement strategy were applied using Xilinx Vivado Design Suite 2023.2. The proposed design architecture was then simulated and implemented on a Xilinx Artix-7 FPGA platform. As a result of this implementation, the propagation delay value of 12.465 ns was obtained by implementing the design using only 165 Lookup Tables (LUTs). The approximate computing framework provides a 99.56% arithmetic accuracy trading minimal precision to eliminate critical path delay and area overheads.

Authors

Shyam Peraka, Vinod Babu Pusuluri, Shanmuga Shruthi Alluru, Vamsi Krishna Sai Avvaru
Rajiv Gandhi University of Knowledge Technologies, India

Keywords

Approximate Computing, Parallel Prefix Adder (PPA), FPGA-Aware Design, Image Fusion, P-Block Floor Planning