Abstract

With the increasing complexity of System-on-Chip (SoC) designs, the demand for efficient and scalable interconnect architecture has become critical. Network-on-Chip (NoC) has emerged as a promising solution for addressing communication bottlenecks in modern SoCs. Traditional NoC topologies often suffer from high latency, low throughput, and inefficient power consumption when scaled to support many-core systems. There is a pressing need for novel topologies that balance performance and energy efficiency. This study proposes a modified hybrid mesh-tree NoC topology (HMT-NoC) designed using Xilinx Vivado and simulated using ModelSim. The architecture aims to reduce average packet latency, increase throughput, and optimize energy usage. Performance is validated through simulations under uniform, hotspot, and bit-complement traffic patterns. The HMT-NoC achieved a 23% reduction in average latency, 18% improvement in throughput, and 12% lower power consumption compared to conventional mesh and torus topologies across various core sizes.

Authors

T. Suresh
R.M.K. Engineering College, India

Keywords

Network-on-Chip, System-on-Chip, Topology Design, Performance Metrics, Low-Latency Communication