Abstract

In the post-Moore's law era, the quest for enhanced computational power has led to exploration beyond traditional electrical digital computing. Integrated Network Interface Cards (NICs) have emerged as a key player in high-performance computing, offering low latency and high bandwidth. To address throughput limitations in Systolic array hardware, a reconfigured software-defined System-on-Chip (SoC) utilizing Advanced Microcontroller Bus Architecture (AMBA) standards is proposed. This study introduces a block data trimming methodology that improves hybrid computing efficiency. The designed Systolic array Matrix Multiply Unit (MMU) is tested with a maximum size of 32 × 32 and 1,024 Multiply Accumulator (MAC) units. Hybrid dynamic circuits are implemented to support int8, int16, int32, and int64 data types, optimizing parallel computing performance. The new AI accelerators exhibit a 2× increase in throughput and a 1.33× improvement in DSP efficiency compared to the previous FireFly version, and achieve 1.42× better power efficiency than the leading FPGA accelerators.

Authors

S. Kaliswaran¹, R. Saranya², Ajeet Kumar Srivastava³, C. Saravanakumar⁴, Deepali Suhas Jadhav⁵
Government Arts and Science College, Perumbakkam, India¹, V.S.B. Engineering College, India², Chhatrapati Shahu Ji Maharaj University, India³, SRM Valliammai Engineering College, India⁴, Vishwakarma Institute of Technology, India⁵

Keywords

FPGA, Systolic Array, AI Accelerators, High-Performance Computing, SoC