Abstract

The design of low power high performance Multiply and Accumulate (MAC) unit is presented in this paper. The power analysis for MAC unit is carried out for image filtering application exploiting insignificant bits in pixel values. The developed technique is found to reduce dynamic power consumption by analyzing the bit patterns in the input data which reduces the switching activities. The power consumption of the developed multiplier is compared with existing multiplier techniques and found that is performs better. It is observed from the simulation using SYNOPSIS EDA tool that the proposed pixel properties reusability technique saves power up to 88% with small area over head when used in MAC unit.

Authors

M. Madheswaran¹ and S. Saravanan²
Muthayammal Engineering College, India

Keywords

Low Power, VLSI Design, Booth Multiplier, MAC