Abstract

This paper describes the development of a Multiprocessor System-on-Chip (MPSoC) with a novel interconnect architecture incorporating memory allocation. It addresses the problem of mapping a process network with data dependent behavior and soft real time constraints onto the heterogeneous multiprocessor System on Chip (SoC) architectures and focuses on a memory allocation step which is based on an integer linear programming model. An application is modeled as Kahn Process Network (KPN) which makes the parallelism present in the application explicit. The main contribution of our work is an MILP based approach which can be used to map the KPN of streaming applications with data dependent behavior and interleaved computation and communication. Our solution minimizes hardware cost while taking into account the performance constraints. One of the salient features of our work is that it takes into account the additional overheads because of data communication conflicts. It permits to obtain an optimal distributed shared memory architecture minimizing the global cost to access the shared data in the application, and the memory cost. Our approach allows automatic generation of an architecture-level specification of the application.

Authors

T.Thillaikkarasi¹, A. Jagadeesan², K.Duraiswamy³
Bannari Amman Institute of Technology, Tamil Nadu, India¹, Bannari Amman Institute of Technology, Tamil Nadu, India², K.S.R.College of Technology, Tiruchengode, Tamil Nadu, India³

Keywords

Application Specific Multiprocessors, Integer Linear Programming, Kahn Process Networks, System on Chip, Memory Allocation