DESIGN OF NOISE TOLERANCE 9T SRAM CELL

Abstract
This paper describes the well-thought-out design of a 9T Static Random Access Memory single Bit cell with enhanced performance. MonteCarlo simulations are utilized for this proposed 9T SRAM circuit, and the outcomes are verified by comparing with various like Conv6T, Conv7T and Conv8T SRAM cells in the 22-nm PTM with variable supply voltage. The proposed 9T SRAM shows 1.02/1.265/ 0.259 × lesser read delay and 1.028/1.032/0.857 × write delay as compared to Conv6T/Conv7T/ Conv8T respectively. Our proposed 9T SRAM showing 2.06/12.5 × less leakage power dissipation as compared to Conv6T/ Conv8T respectively.

Authors
Chandramuleswar Roy1,Naveen2,Jaswanth Achari3,Naresh K. Reddy4
Madanapalle Institute of Technology and Science, India1,2,3,4

Keywords
Read Access Time, Write Access Time, Read SNM, Read Power, Write Power, Hold Power
Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 8 , Issue: 2 )
Date of Publication :
July 2022
DOI :

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