HARDWARE SECURITY MODEL WITH VEDIC MULTIPLIER BASED ECC ALGORITHM ON HIGH-PERFORMANCE FPGA DEVICE

Abstract
The key problem that the world is most concerned about is security. Data security is the process of preventing unauthorized access to sensitive data. It includes all of the cybersecurity measures you take to keep your data safe from unauthorized access, such as encryption and access restrictions (both physical and digital). Data security has always been of the utmost importance. We utilize cryptographic methods to improve the services of data security. The application of cryptographic algorithms achieves data encryption. Therefore, we developed two versions of ECC algorithms on FPGA for improved hardware security in this study. The FPGA device employed here is Kintex-7, and there are two types of ECC: standard ECC and Vedic multiplier-based ECC. Vedic multiplier-based ECC has discovered that it consumes less space than standard ECC. Not only does Vedic multiplier-based ECC save space, but it also saves electricity. As a result, it is determined that for improved hardware security with ECC enabled, Vedic Multiplier-based ECC should be used over standard ECC.

Authors
Saurabh Singh, Sunita Soni
Bhilai Institute of Technology, India

Keywords
ECC, Vedic Multiplier based ECC, Area, Power, and FPGA
Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 8 , Issue: 1 )
Date of Publication :
April 2022
DOI :

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