ARCHITECTURAL DESIGN AND OPTIMIZATION OF DISTRIBUTED ARITHMETIC BASED 2-D DISCRETE COSINE TRANSFORM

Abstract
DCT is immensely used in Multimedia applications because it provides high energy compaction. The proposed architectural design of 1D-DCT employs an efficient computational technique, Distributed arithmetic and is synthesized using front end VLSI technique. The motive of utilising Distributed arithmetic is to have multiplier-less architecture that reduces the Area-delay product in comparison to the multiplier-based design by retaining the same structural regularities. The symmetric property of the DCT kernel matrix is applied to develop the proposed architecture which reduces the requirements of a number of multiplications by almost 50%. The 1D-DCT architecture is extended to 2D-DCT using only N 1D-DCT modules, while the conventional row-column decomposition method requires 2N 1D-DCT modules. The proposed 2D-DCT architecture is designed and implemented on a 65nm LX110T device of Vertex-5 FPGA and its performance evaluation is carried out. The debug and verification process has been carried out using the Virtual input-output technique. The results show improvement in delay and area consumption in contrast with existing models.

Authors
Shrikanth Shirakol, S S Kerur
SDM College of Engineering and Technology, India

Keywords
Dimensional Discrete cosine transform (1D-DCT), Distributed arithmetic (DA), Multiply and accumulate (MAC), Field programmable gate array (FPGA)
Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 8 , Issue: 1 )
Date of Publication :
April 2022
DOI :

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