LITERATURE SURVEY ON AREA OPTIMIZATION OF CMOS FULL ADDER DESIGN

Abstract
In this paper, a novel architecture for a dynamic logic-based full adder is introduced and analyzed. In full adder architecture, the XOR and XNOR gates are commonly employed as basic logic units. In the report, improved XOR and XNOR logic gate topologies are employed to produce a full adder circuit. The envisioned XOR/XNOR gate architecture has a full logic cycle. The suggested adder design is modelled using a traditional 180 nm CMOS technique. The simulated outcomes using the SPICE simulation tool demonstrated that the proposed network has significant advantages in energy loss and efficiency while compared to previously published designs.

Authors
Dolly Thakur1,Hemant Patidar2
Oriental University, India1,Oriental University, India2

Keywords
MOS Current-Mode Logic (MCML), Ternary Full-Adder (TFA), Low Power, Gate-Diffusion-Input (GDI), Ripple Carry Adder (RCA
Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 7 , Issue: 4 )
Date of Publication :
January 2022
DOI :

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