Abstract
Data and hardware security are crucial in modern electronics, leading
to increased adoption of Physically Unclonable Functions (PUFs) to
generate unique circuit signatures. Conventional PUF designs face
challenges in fault tolerance and reliable performance under varying
conditions. This paper introduces a fault-tolerant system integrating a
ring-oscillator (RO) based PUF with a reversible logic (RL) design and
a Deep Neural Network (DNN). The system consists of a Fault-
Tolerant RL-based inverter design, Reversible-Logic designing, Fault-
Detection module, Fault-free path selection module, and the Reversible
RO-PUF module. The implementation is carried out on a Basys-3
FPGA board. The proposed system achieved a PUF uniqueness of
99.5%, stability of 98.7%, and reliability of 97.3%. Fault detection
accuracy reached 95.2%, with a fault-tolerant rate of 96.1%.
Authors
Sanjay Laxmanrao Kurkute1, Sumana De2, Vishwayogita Savalkar3, Vandana B. Salve4, Dinesh Kumar Gupta5, Khaled A. A. Alloush6
Pravara Rural Engineering College, India1, C V Raman Global University, India2, Bharati Vidyapeeth, India3, K J Somaiya Institute of Technology, India4, Mahant Bachittar Singh College of Engineering and Technology, India5, Arab Open University, Saudi Arabia6
Keywords
Physically Unclonable Function, Reversible Logic, Deep Neural Network, FPGA, Fault Tolerance