The Digital signal processing plays a vital role in communication applications. In Digital signal processing, ALU is an important functional unit. The main objectives of VLSI architecture design are the speed and power. Here we are going to design low power, high speed ALU by using vedic mathematics technique. This paper describes the design of more efficient high speed 4 × 4 bit arithmetic logic unit based on Vedic multiplication technique. It can perform arithmetic and logical operations. Generally the digital domain based design depends on the performance of ALU and hence the high performance ALU is predominant. The ALU speed is mainly based on the speed of multiplier. There are so many algorithms used for multiplication technique. Our work has proved that Vedic multiplication technique is the best algorithm in terms of speed. The Vedic multiplication algorithm is based on 16 sutra. Here we are using Urdhva Tiryakbhyam [1].The 4-bit ALU was designed using Vedic mathematics and the performance compared with 4-bit Array multiplier based ALU. The ALU which is shown here is very efficient in terms of speed and power dissipation.
R. Jaikumar1, P. Poongodi2, R. Lavanya3
RVS college of Engineering and Technology, India1, VSB Engineering College, India2, Sri Ranganathar Institute of Engineering and Technology, India3
Vedic Mathematics, Low Power, Urdhva Tiryakbhyam, Speed | Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 1 , Issue: 1 )
Date of Publication :
February 2015
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