NOVEL LOW-POWER CMOS VLSI DESIGN USING FEDERATED LEARNING BASED ADIABATIC SWITCHING PRINCIPLE
Abstract
This research introduces a groundbreaking approach to low-power CMOS VLSI design by leveraging the principles of federated learning and adiabatic switching. The escalating demand for energy-efficient integrated circuits necessitates innovative methodologies to mitigate power consumption while maintaining performance. Existing VLSI designs often face challenges in achieving optimal power efficiency, resulting in a research gap that this study aims to address. Our proposed method integrates federated learning, a decentralized machine learning paradigm, with the adiabatic switching principle, which involves gradual energy transitions. By employing federated learning for optimizing power consumption at distributed nodes and implementing adiabatic switching for energy-efficient transitions between logic states, the novel VLSI design promises to revolutionize low-power consumption in CMOS circuits. Results from simulations and experiments demonstrate substantial reductions in power consumption without compromising performance. The federated learning-based adiabatic switching principle achieves a significant breakthrough in low-power VLSI design, offering a viable solution to the current challenges in energy efficiency. This research paves the way for the development of next-generation, environmentally friendly integrated circuits with improved power efficiency and performance.

Authors
J. Muralidharan1, Manasi Dnyanesh Karajgar2, N. Kanagavalli3, S. Sudha4
KPR Institute of Engineering and Technology, India1, D Y Patil College of Engineering, India2, Rajalakshmi Institute of Technology, India3, Sri Ranganathar Institute of Engineering and Technology, India4

Keywords
Low-Power CMOS, VLSI Design, Federated Learning, Adiabatic Switching, Energy Efficiency
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Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 9 , Issue: 4 , Pages: 1693 - 1699 )
Date of Publication :
January 2024
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93
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