The Power Consumption (PC) of VLSI circuits is a crucial reason that requires careful consideration especially for packages that must have the lowest possible strength. Power dissipation in Flip-Flops (FF) and clock distribution networks must be minimized because contemporary portable digital circuits have a very constrained strength budget. Additionally, because of the limited time finances at high frequency operation turn-flop latency must be minimized. Thus it is crucial to design with low latency and electricity intake in mind when using current VLSI generation. A processors clocking mechanism is mainly made up of clock supply networks and Flip-Flops (FF). Because the alternative clock part is designed for data processing the traditional single-phase clock FFs method introduces statistics by using the best clock part at a time causing a redundant strength overhead. Dual edge-triggering (DET) FFs use each clock edge (CE) to technique facts permitting them to cut the clock frequency in half by preserving throughput. To address these issues a useful dual-edge-triggering (DET) FF that eliminates clock redundant transitions (RTs) entirely and improves performance through feel amplification is proposed. The first of its kind to totally eliminate the clock and inner redundant switching is the proposed DET FF. FF design employs zero redundant transition (RT) single-transistor-clocked (STC). A sensing amplifier primarily based flip-flop (SAFF) that can operate dependably over a broad voltage and temperature range is included in this painting. Similar to a differential sensing stage turn flops that are primarily based on feel amplifiers have a slave latching degree. The purpose of the sensing degree is to report information at the rising Edge (RE)and falling edges (FE) of the clock while the sense amplifiers output is sustained for the duration of the clocks effective half cycle. Consequently, the size restrictions associated with traditional pulse-precipitated flip-flops are eliminated. SAFF (Sense-Amplifier FF) has various capabilities such as reduced clock load shorter hold intervals and a poor or almost zero setup time. SAFFs outperform pulse-induced turn flips and master slave flip flips when it comes to low voltage operation. Utilizing 22 nm CMOS technology the cautioned hybrid layout is designed using the MICROWIND device. Power-delay-product (PDP) and proximity electricity delay are compared between the current DET designs and the proposed design.
K. Mahendrakan, B. Paulchamy, R. Vaishnavi, A. Roopa Sree
Hindusthan Institute of Technology, India
Power Consumption, GDI technique, Universal Gates, FD-SOI and PDP
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 11 , Issue: 1 , Pages: 1983 - 1988 )
Date of Publication :
April 2025
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14
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