Modern CMOS processors face a significant challenge in power
consumption, primarily due to switching and leakage power. With
rising demands for energy-efficient systems, especially in mobile and
IoT devices, managing dynamic and static power has become essential.
Conventional clock gating techniques lack adaptability to workload
variability, leading to inefficient power savings. Fixed gating schemes
either over-constrain performance or underperform in power savings.
This work proposes a Low-Power Reconfigurable Match Table (RMT)-
based Clock Controller that dynamically adjusts clock gating
granularity based on real-time workload profiling. The system
leverages a match table reconfiguration mechanism, enabling fine-
grained control of clock signals to idle submodules. Implemented in a
45nm CMOS processor simulation environment, this approach
combines workload prediction and table-driven reconfiguration for
minimal leakage and switching overhead. Simulation results show a
38.6% reduction in switching power and a 29.3% reduction in leakage
power compared to traditional fixed clock gating, with only 1.2%
performance overhead. Power savings remain consistent across varied
computational loads.
Joby Titus
Sri Krishna College of Engineering and Technology, India
CMOS Processor, Power Optimization, Clock Gating, Leakage Power, Reconfigurable Controller
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 11 , Issue: 1 , Pages: 2011 - 2018 )
Date of Publication :
April 2025
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