Abstract

In deep sub-micron memories like DRAM and SRAM, faithful sensing of bit line voltages is becoming very challenging as transistor characteristics mismatch caused by intrinsic variations in manufacturing processes has posed a grave challenge leading to failures of circuits and reductions in yield. This paper addressed these issues and applied a compensation scheme to various schematics of sense amplifiers, which have resulted in a high tolerance to process-induced variations. The schematics, designed with DGFinFET, utilize an enhanced self-compensation technique to surmount disparities in physical transistor characteristics. The recreations of transistor mismatch (threshold voltage, Vt) using the Monte-Carlo technique show that the proposed CCLSA schematic performs correctly even for severe Vt mismatch of 40-50mV. These results are compared with corresponding circuits reported in the literature for the speed, area, and yield. This design also offers up to 20-30% higher yield compared to its uncompensated counterpart and has a reduced penalty for the complexity of circuit and performance. These circuits are easily implementable at 45nm and 32nm technology nodes.