ANALYSING THE PERFORMANCE TRADEOFFS OF PARAMETERIZED VLSI ARCHITECTURE USING TREE-LOGIC MACHINE LEARNING SYSTEM

ICTACT Journal on Microelectronics ( Volume: 9 , Issue: 1 )

Abstract

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This paper deals with the design of a tree logic machine learning system agent that is based on a hybrid technique that blends graph handmade properties with graph neural network embeddings. It is a combination of traditional reinforcement learning and deep learning that involves the substitution of tree logic machine learning system in the learning process. The proposed agent uses a new EMAC-TLML system that is compatible with the inference made by deep learning networks that use 8 bits of precision, and we demonstrate that this compatibility works quite well. It has been demonstrated that the proposed research uses resources and produces energy delay products in a manner that is analogous to that of their floating-point counterparts. The solution that has been suggested provides a greater maximum working frequency in contrast to the floating-point method.

Authors

T. Gobinath1, A. Sumalatha2, M. Kumar3, M. Dharani4
Chettinad College of Engineering and Technology, India1, Kristu Jayanti College, India2, Chettinad College of Engineering and Technology, India3, KSR Institute for Engineering and Technology, India4

Keywords

Machine Learning, Tree Logic, Performance Trade-off, VLSI

Published By
ICTACT
Published In
ICTACT Journal on Microelectronics
( Volume: 9 , Issue: 1 )
Date of Publication
April 2023
Pages
1498 - 1502

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