Abstract

This paper presents the results of a study that utilises genetic algorithms to optimise the scheduling of tests for a core-based systemon-chip (SoC) system. The research aims at reducing the amount of time that is required to test a SoC system, as well as ensuring that a system meets the requirements of the design. The findings show that it is possible to locate networks that have been carefully tailored to meet the requirements outlined by the RT packets with relation to latency, area, and deadline. The results show that the irregular networks with heterogeneous routers fared much better than the mesh networks when it comes to performance and compliance with the design requirements.