vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff648f2c000000c616060001000800 Multiple adders and multipliers make up a complex digital signal processing system (DSP). The efficient design of adders and multipliers improves the DSP system performance. In this paper, modified 4-Tap digital Finite Impulse Response (FIR) filter is built using the Pipelined Brent-Kung adder (PBKA) and a Vedic multiplier. The top-level module (FIR filter) is created by writing PBKA and PBKA-based Vedic multiplier Verilog code. The results of Pipelined Brent Kung adderbased FIR filter are compared with BKA and KSA-based 4-Tap digital FIR filter. According to the synthesis results, the PBKA-based FIR filter operates 57% faster than the BKA-based FIR filter. In terms of Power Delay Product (PDP) PBKA based FIR filter is 22% efficient than BKA based FIR filter. Xilinx 14.7 ISE software is used for simulation, while Virtex-7 FPGA is used for synthesis.
Basavoju Harish1,M.S.S. Rukmini2,K. Sivani3
Vignan's Lara Institute of Technology and Science, India1,2,Kakatiya Institute of Technology and Science, India3
Brent Kung Adder, FIR Filter, Kogge Stone Adder, Parallel Prefix Adder, Pipelined Brent Kung Adder, Vedic Multiplier, Virtex 7 FPGA
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 8 , Issue: 2 , Pages: 1334-1337 )
Date of Publication :
July 2022
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173
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